HAL, Inc. is a major manufacturer of computers and computer components Essay

HAL, Inc. is a major manufacturer of computers and computer components. In one of their plants they made printed circuit boards (PCB’s), which were used by other plants in the company in a variety of computer products. The basic process runs 3 shifts per day and it can be briefly depicted by following flow diagram Optical Test-internal Pro-Coat Copper plate Drilling Optical Test- external End of line test Sizing Machining Lamination core Treater procMess Internal circuitize Lamination composite External circuitize The targeted output for the plant is 3000 boards per day, five days a week, with plant running three shifts per day. But the plant has been failed to reach and maintain the targeted throughput at a steady rate due to manufacturing complexities associated with the product mix. It was also found that, the output of the pro-coat process is very slow (1200 boards/day) compared to the expected throughput and therefore Hal has to engage a vendor on the pro- coat process to fulfil the demand. This engagement of vendor has caused increase in cost per board and two days delay because of shipping up and back. So the Hal is striving to increase the throughput of the pro-coat process and the purpose of this case study is to provide some guidance to them in their effort by giving some recommendations to improve the existing system. Floor arrangement and the work flow of the pro-coat process Daily demand = 3000 boards Working hours = 24- (Breaks + Lunch + shift change + Meeting) = 24-(20X2X3+40X3+10X3+90/5) = 19.2 hrs Demand= 3000/(19.2X60) = 2.604 boards/min Assumption; 1. Demand = Arrival rate (ra=2.604 boards/min) 2. Arrival pattern exponentially distributed (Ca2=1) Machine Name| Mean process (load) time (min)| Std. Dev. Process Time (min)| Trip Time (conveyor) (min)| MTBF (hr)| MTTR (hr)| Setup time (min)| Availability| Number of machines| Rate per day| Clean| 0.33| 0| 15| 80| 4| 0| 0.95238| 1| 3325| Coat 1| 0.33| 0| 15| 80| 4| 0| 0.95238| 1| 3325| Coat 2| 0.33| 0| 15| 80| 4| 0| 0.95238| 1| 3325| Expose| 103| 67| 0| 300| 10| 15| 0.96774| 5| 2834| Develop| 0.33| 0| 2.67| 300| 3| 0| 0.99010| 1| 3456| Inspect| 0.5| 0.5| 0| 0| 0| 0| 1.00000| 2| 4608| Bake| 0.33| 0| 100| 300| 3| 0| 0.99010| 1| 3456| MI| 161| 64| 0| 0| 0| 0| 1.00000| 8| 3435| Touchup| 9| 0| 0| 0| 0| 0| 1.00000| 1| 7680| Once analysed the Hal pro coat process, the expose work station (highlighted in above table) has been found as bottle neck operation under the 19.2 working hour situation. But the company goal is to achieve 3000 boards per day. If the company operate under the optimum condition, 2,834 boards could be produces, which is still below the company goal. According to the given data in the case was deeply analysed as follow. Assumption: Inspection and MI are manual operations. So number of work benchers has been considered as 8 in MI operation and 2 in inspection work station. It could be possible to eliminate the bottleneck situation by adding resource (No of operators). 1. Cleaning Effective processing time (te) = t0A = 0.33/0.95238 = 0.3465 min Utilization (u) = rax te = 2.604 X 0.3465 = 0.902 Ce2= C02+1+Cr2A(1-A)mrt0 Ce2= o+1+00.95238(1-0.95238)2400.33 = 32.98 Departure rate; Cd2=u2Ce2+(1-u2)Ca2 = 0.9022x 32.98+1-0.9022x 1 = 27.019 cd2 =27.019 2. Coat 1 Similarly, Effective processing time (te) = 0.3465 min Utilization = 0.902 Ce2= C02+1+Cr2A(1-A)mrt0 ce 2 =32.98 Cd2=u2Ce2+(1-u2)Ca2 = 0.9022x 32.98+1-0.9022x 27.019 cd2=31.87 3. Coat 2 Similarly, Effective processing time (te) = 0.3465 min Utilization = 0.902 Ce2= C02+1+Cr2A(1-A)mrt0 ce2 =32.98 Cd2=u2Ce2+(1-u2)Ca2 = 0.9022x 32.98+1-0.9022x 31.87 cd2=32.77 4. Coating and expose Since the coating 2 processing rate greater than the arrival rate of the pro- coat system. Arrival rate of the expose machine govern by the arrival rate of pro-coat system Expose machine calculations based on jobs (60 boards = 1 job) Arrival rate =2.604/60 =0.0434 jobs/min Buffer size = 05 Blocking size = (buffer size + maximum jobs in expose machines) = 5 + 5 b = 10 ra=0.0434 Ca2=32.77 Coating 2 Expose = 10 Preemptive outages; Effective processing time (te) = t0A = 103/0.9677 = 106.43 min Assumption; Number of boards between setups = 120 Total effective processing time (Preemptive and Non-preemptive outages); (te) = t0A+tsNsx job size = 1.720.9677+15120x 60 = 114.14 min Assumption – Standard deviation for repair = 0 min (constant distribution) Preemptive outage variance = ÏÆ'02A2+(mr2+ÏÆ'r2)(1-A)t0Amr =672.96772+6002+01-0.9677Ãâ€"1030.9677Ãâ€"600 = 6856.43 Preemptive outage SCV Ce2= C02+1+Cr2A(1-A)mrt0 = 6721032+1+0x0.9677Ãâ€"1-.9677Ãâ€"600103 =0.6052 Assumption- No variation in setups (constant distribution) Total variance (preemptive + non-preemptive outage) = ÏÆ'02+ÏÆ's2Ns+(Ns-1)Ns2ts2 = 6856.43+0+(120-1)1202152 =6858.29 SCV for expose(preemptive + non-preemptive outage) = =Ce2= ÏÆ'e2te2 = 6858.29114.142 = 0.526 Utilization for expose = raxtem = 0.0434Ãâ€"114.145 =0.99 Arrival SCV for batch = Arrival SCV for individual part/batch size = 32.7760 = 0.546 U